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| ? 2010 microchip technology inc. ds39991a-page 1 pic24fxxka2xx 1.0 device overview this document defines the programming specifications for the pic24fxxka2xx family of 16-bit micro- controller devices. this is required only for developing programming support for the pic24fxxka2xx family. users of any one of these devices should use the development tools that are already supporting the device programming. the programming specifications are specific to the following devices: ? PIC24F04KA200 ? pic24f04ka201 2.0 programming overview of the pic24fxxka2xx family pic24fxxka2xx family devices are programmed exclusively using in-circuit serial programming? (icsp?). this method provides native, low-level pro- gramming capability to erase, program and verify the device. section 3.0 ?icsp programming? describes the icsp method. 2.1 power requirements all devices in the pic24fxxka2xx family are 3.3v supply designs. the core, the peripherals and the i/o pins operate at 3.3v. the device can operate from 1.8v to 3.6v. table 2-1 provides the pins that are required for programming, which are indicated in figure 2-1 . refer to the device data sheet for complete pin descriptions. table 2-1: pin descriptions (during programming) note: unlike other pic24f devices, pic24fxxka2xx devices do not support enhanced icsp programming. these devices also do not support in-circuit debugging over the icsp interface. pin name during programming pin name pin type pin description mclr /v pp mclr /v pp p programming enable v dd v dd p power supply v ss v ss pground pgcx pgc i programming pin pair: serial clock pgdx pgd i/o programming pin pair: serial data legend: i = input, o = output, p = power pic24fxxka2xx flash programming specifications
pic24fxxka2xx ds39991a-page 2 ? 2010 microchip technology inc. figure 2-1: pic24fxxka2xx pin diagrams pic24xxka201 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin spdip, soic mclr/ v pp pgc2 pgd2 pgc3 pgd3 v dd v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14-pin spdip, soic mclr/ v pp pgc2 pgd2 pgc3 pgd3 v dd v ss PIC24F04KA200 89 2 3 1 12 13 14 15 10 6 11 16 17 18 19 20 7 pic24f04ka201 5 4 mclr /v pp pgc2 pgd2 v dd v ss pgc3 pgd3 20-pin qfn ? 2010 microchip technology inc. ds39991a-page 3 pic24fxxka2xx 2.2 memory map the program memory map extends from 000000h to fffffeh. code storage is located at the base of the memory map, and supports up to about 1.38 k words of instructions (about 4 kbytes). figure 2-2 depicts the memory map. table 2-2 provides the program memory size and number of program memory rows present in each device variant. the erase operation can be done on one word, half of a row or one row at a time. the program operation can be done only one word at a time. the device configuration registers are implemented from location, f80000h to f80010h, and can be erased or programmed one register at a time. tab l e 2 - 3 pro- vides the implemented configuration registers and their locations. locations, ff0000h and ff0002h, are reserved for the device id registers. these bits can be used by the programmer to identify the device type that is being programmed. see section 4.0 ?device id? for more information. the device id registers read out normally even after code protection is applied. table 2-2: program memory sizes table 2-3: config uration register locations figure 2-2: program memory map device program memory upper address (instruction words) rows PIC24F04KA200 afeh (1.375k) 44 pic24f04ka201 configuration register address fgs f80004 foscsel f80006 fosc f80008 fwdt f8000a fpor f8000c ficd f8000e fds f80010 000000h code memory configuration memory space (2816 x 24-bit) 800000h device id fefffeh ff0000h fffffeh reserved reserved 8007f0h ff0002h ff0004h reserved (2 x 16-bit) user flash 8007eeh configuration registers f80010h f80000h diagnostic words 800800h 8007feh 000afeh user memory space reserved pic24fxxka2xx ds39991a-page 4 ? 2010 microchip technology inc. 3.0 icsp programming the icsp method is a special programming protocol that allows reading and writing to the pic24fxxka2xx device family memory. this is accomplished by apply- ing control codes and instructions, serially to the device, using pgcx and pgdx pins. in icsp mode, the system clock is taken from the pgcx pin, regardless of the device?s oscillator configuration bits. all of the instructions are shifted serially to an internal buffer, loaded into the instruction register (ir) and then executed. no program is fetched from the internal memory. instructions are fed in 24 bits at a time. pgdx is used to shift data in, and pgcx is used as both the serial shift clock and the cpu execution clock. 3.1 overview of the programming process figure 3-1 illustrates the high-level overview of the programming process. after entering the icsp mode, perform the following: 1. bulk erase the device. 2. program and verify the code memory. 3. program and verify the device configuration. 4. program the code-protect configuration bits if required. 3.2 icsp operation upon entry into icsp mode, the cpu is idle. an internal state machine governs the execution of the cpu. a 4-bit control code is clocked in, using pgcx and pgdx, and this control code is used to command the cpu (see tab le 3 - 1 ). the six control code is used to send instructions to the cpu for execution, and the regout control code is used to read data out of the device via the visi register. figure 3-1: high?level icsp? programming flow table 3-1: cpu control codes in icsp? mode note: during icsp operation, the operating frequency of pgcx should not exceed 8mhz. 4-bit control code mnemonic description 0000 six shift in 24-bit instruction and execute. 0001 regout shift out the visi (0784h) register. 0010-1111 n/a this is reserved. start perform bulk erase program memory verify program end enter icsp? mode program configuration bits verify configuration bits exit icsp mode ? 2010 microchip technology inc. ds39991a-page 5 pic24fxxka2xx 3.2.1 six serial instruction execution the six control code allows execution of pic24fxxka2xx family assembly instructions. when the six code is received, the cpu is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. once the instruction is shifted in, the state machine allows it to be executed over the next four pgc clock cycles. while the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see figure 3-2 ). coming out of reset, the first 4-bit control code is always forced to six and a forced nop instruction is executed by the cpu. five additional pgcx clocks are needed on start-up; thereby, resulting in a 9-bit six command, instead of the normal 4-bit six command. after the forced six is clocked in, the icsp operation resumes to normal. that is, the next 24 clock cycles load the first instruction word to the cpu. 3.2.1.1 differences between six instruction execution and normal instruction execution there are some differences between executing instructions using the six icsp command and normal device instruction execution. as a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. the differences are: ? two-word instructions require 2 six operations to clock in all the necessary data. examples of two-word instructions are: goto and call . ? two-cycle instructions require 2 six operations to complete. the first six operation shifts in the instruction and begins to execute it. a second six operation, which should shift in a nop to avoid losing data, allows the cpu clocks required to finish executing the instruction. examples of two-cycle instructions are table read and table write instructions. ? the cpu does not automatically stall to account for pipeline changes. a cpu stall occurs when an instruction modifies a register, which is used by the instruction immediately following the cpu stall for indirect addressing. during normal operation, the cpu forces a nop while the new data is read. to account for this, while using icsp, any indirect references to a recently modified register should be proceeded with a nop . for example, mov #0x0,w0 followed by mov [w0] , w1 must have a nop inserted in between. if a two-cycle instruction modifies a register, which is used indirectly, it requires two following nop s; one to execute the second half of the instruction and the other to stall the cpu to correct the pipeline. for example, tblwtl [w0++] , [w1] should be followed by 2 nop s. ? the device program counter (pc) continues to automatically increment during the icsp instruction execution, even though the flash memory is not being used. as a result, it is possible for the pc to be incremented so that it points to invalid memory locations. examples of invalid memory spaces are unimplemented flash addresses or the vector space (location 0x0 to 0x1ff). if the pc ever points to these locations, it causes the device to reset, possibly interrupting the icsp operation. to prevent this, instructions should be periodically executed to reset the pc to a safe space. the optimal method of achieving this is to perform a ? goto 0x200 ?. 3.2.2 regout serial instruction execution the regout control code allows for the data to be extracted from the device in the icsp mode. it is used to clock the contents of the visi register out of the device over the pgdx pin. after the regout control code is received, the cpu is held idle for 8 cycles. after this, an additional 16 cycles are required to clock the data out (see figure 3-3 ). the regout code is unique as the pgdx pin is an input when the control code is transmitted to the device. however, after the control code is processed, the pgdx pin becomes an output as the visi register is shifted out. note: to account for this forced nop , all example codes in this specification begin with a nop to ensure that no data is lost. note 1: after the contents of visi are shifted out, the pic24fxxka2xx devices maintain pgdx as an output until the first rising edge of the next clock is received. 2: data changes on the falling edge and latches on the rising edge of pgcx. for all data transmissions, the least significant bit (lsb) is transmitted first. pic24fxxka2xx ds39991a-page 6 ? 2010 microchip technology inc. figure 3-2: six serial execution figure 3-3: regout serial execution p4 23 123 2324 1 2 3 4 p1 pgcx p4a pgdx 24-bit instruction fetch execute pc ? 1, 16 0000 fetch six 456 78 1819202122 17 lsb x x x x x x x x x x x x x x msb pgdx = input p2 p3 p1b p1a 78 9 0000 00 0 only for program memory entry control code 4 5 execute 24-bit instruction, fetch next control code 00 1234 1278 pgcx p4 pgdx pgdx = input execute previous instruction, cpu held in idle shift out visi register<15:0> p5 pgdx = output 123 1234 p4a 11 13 15 16 14 12 no execution takes place, fetch next control code 0 0000 pgdx = input msb 1234 1 456 lsb 14 13 12 ... 11 10 0 fetch regout control code 0 ? 2010 microchip technology inc. ds39991a-page 7 pic24fxxka2xx 3.3 entering icsp mode 3.3.1 low-voltage icsp entry as illustrated in figure 3-4 , the following processes are involved in entering icsp program/verify mode using mclr : 1. mclr is briefly driven high, then low. 2. a 32-bit key sequence is clocked into pgdx. 3. mclr is then driven high within a specified period of time and held. the programming voltage, v ih , is applied to mclr ; this is v dd in the case of pic24fxxka2xx devices. there is no minimum time requirement for holding at v ih . after v ih is removed, an interval of at least p18 must elapse before presenting the key sequence on pgdx. the key sequence is a specific 32-bit pattern: ? 0100 1101 0100 0011 0100 1000 0101 0001 ? (more easily remembered as 4d434851h in hexadecimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit (msb) of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as the program/verify mode is to be maintained. an interval of at least p19 and p7 must elapse before presenting data on pgdx. signals appearing on pgcx before p7 has elapsed would not be interpreted as valid. 3.3.2 high-voltage icsp entry entering the icsp program/verify mode, using the v pp pin is the same as entering the mode using mclr . the only difference is the programming voltage applied to v pp is v ihh , and before presenting the key sequence on pgdx, an interval of at least p18 should elapse (see figure 3-5 ). once the key sequence is complete, an interval of at least p7 should elapse, and the voltage should remain at v ihh . the voltage, v ihh , must be held at that level for as long as the program/verify mode is to be main- tained. an interval of at least p7 must elapse before presenting the data on pgdx. signals appearing on pgdx before p7 has elapsed will not be interpreted as valid. upon a successful entry, the program memory can be accessed and programmed in serial fashion. while in icsp mode, all unused i/os are placed in a high-impedance state. figure 3-4: entering icsp? mode using low-voltage entry figure 3-5: entering icsp? mode using high-voltage entry mclr pgdx pgcx v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434851h p1a p1b p18 p19 0100 0 0 p7 v ih v ih 1 0 1 v pp pgdx pgcx v dd p6 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434851h p1a p1b p18 0100 0 0 1 0 1 v ihh v ih p7 pic24fxxka2xx ds39991a-page 8 ? 2010 microchip technology inc. 3.4 flash memory programming in icsp mode 3.4.1 programming operations the nvmcon register controls the flash memory write and erase operations. to program the device, set the nvmcon register to select the type of erase operation (see table 3-2 ) or write operation (see table 3-3 ). set the wr control bit (nvmcon<15>) to initiate the program. in icsp mode, all programming operations are self-timed. there is an internal delay between setting and automatic clearing of the wr control bit when the programming operation is complete. refer to section 5.0 ?ac/dc characteristics and timing requirements? for information on the delays associated with various programming operations. 3.4.2 starting and stopping a programming cycle the wr bit (nvmcon<15>) is used to start an erase or write cycle. initiate the programming cycle by setting the wr bit. all erase and write cycles are self-timed. the wr bit should be polled to determine if the erase or write cycle is completed. start a programming cycle as follows: bset nvmcon, #wr table 3-3: nvmcon values for write operations table 3-2: nvmcon values for erase operations nvmcon value erase operation 4064h erase the code memory and configuration registers (does not erase programming executive code and device id registers). 404ch erase the general segment and configuration bits associated with it. 4068h erase the boot segment and configuration bits associated with it. 405ah (1) erase four rows of code memory. 4059h (1) erase two rows of code memory. 4058h (1) erase a row of code memory. 4054h erase all the configuration registers (except the code-protect fuses). 4058h (1) erase configuration registers except fbs and fgs. note 1: the destination address decides the region (code memory or configuration register) of the erased rows/words. nvmcon value write operation 4004h (1) write one configuration register. 4004h (1) program one row (32 instruction words) of code memory or executive memory. note 1: the destination address decides the region (code memory or configuration register) of the erased rows/words. ? 2010 microchip technology inc. ds39991a-page 9 pic24fxxka2xx 3.5 erasing program memory to erase the program memory (all of code memory, data memory and configuration bits, including the code-protect bits), set the nvmcon to 4064h and then execute the programming cycle. figure 3-6 illustrates the icsp programming process for bulk erase. this process includes the icsp command code, which must be transmitted (for each instruction), lsb first, using the pgcx and pgdx pins (see figure 3-2 ). table 3-4 provides the steps for executing serial instruction for the bulk erase mode. figure 3-6: bulk erase flow table 3-4: serial instruction execution for chip erase note: program memory must be erased before writing any data to program memory. end set the wr bit to initiate erase write 4064h to nvmcon sfr delay p11 + p10 time start command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: set the nvmcon to erase the entire program memory. 0000 0000 24064a 883b0a mov #0x4064, w10 mov w10, nvmcon step 3: set the tblpag and perform dummy table write to select the erased memory. 0000 0000 0000 0000 0000 0000 200000 880190 200000 bb0800 000000 000000 mov # pic24fxxka2xx ds39991a-page 10 ? 2010 microchip technology inc. 3.6 writing code memory the procedure for writing code memory is the same as writing the configuration registers. the difference is that the 32 instruction words are programmed one at a time. to facilitate this operation, working registers, w0:w5, are used as temporary holding registers for the data to be programmed. figure 3-8 illustrates the code memory writing flow. table 3-5 provides the icsp programming details, including the serial pattern with the icsp command code, which must be transmitted, lsb first, using the pgcx and pgdx pins (see figure 3-2 ). in step 1 of tab le 3 - 5 , the reset vector is exited. in step 2, the nvmcon register is initialized for programming a full row of code memory. in step 3, the 24-bit starting destination address for programming is loaded into the tblpag register and w7 register. the upper byte of the starting destination address is stored in tblpag and the lower 16 bits of the destination address are stored in w7. to minimize the programming time, a packed instruction format is used (see figure 3-7 ). in step 4 of tab le 3 - 5 , four packed instruction words are stored in working registers, w0:w5, using the mov instruction; the read pointer, w6, is initialized. figure 3-7 illustrates the contents of w0:w5 holding the packed instruction word data. in step 5, eight tblwt instructions are used to copy the data from w0:w5 to the write latches of the code memory. since code memory is programmed 32 instruction words at a time, steps 3 to 5 are repeated eight times to load all the write latches (see step 6). after the write latches are loaded, initiate programming by writing to the nvmcon register in steps 7 and 8. in step 9, the internal pc is reset to 200h. this is a precautionary measure to prevent the pc from incrementing to unimplemented memory when large devices are being programmed. finally, in step 10, repeat steps 3 through 9 until all of the code memory is programmed. figure 3-7: packed instruction words in w0:w5 15 8 7 0 w0 lsw0 w1 msb1 msb0 w2 lsw1 w3 lsw2 w4 msb3 msb2 w5 lsw3 table 3-5: serial instruction ex ecution for writing code memory command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: set the nvmcon to program 32 instruction words. 0000 0000 24004a 883b0a mov #0x4004, w10 mov w10, nvmcon step 3: initialize the write pointer (w7) for tblwt instruction. 0000 0000 0000 200xx0 880190 2xxxx7 mov # ? 2010 microchip technology inc. ds39991a-page 11 pic24fxxka2xx step 4: load w0:w5 with the next 4 instruction words to program. 0000 0000 0000 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 mov # pic24fxxka2xx ds39991a-page 12 ? 2010 microchip technology inc. figure 3-8: program code memory flow start write sequence all locations done? no end start yes load 2 bytes to write buffer at ? 2010 microchip technology inc. ds39991a-page 13 pic24fxxka2xx 3.7 writing configuration registers the procedure for writing the configuration registers is the same as for writing code memory. the only differ- ence is that only one word is programmed in each operation. when writing conf iguration registers, one word is programmed during each operation. only work- ing register, w0, is used as a temporary holding register for the data to be programmed. table 3-6 provides the default values of the configuration registers. table 3-6 provides the icsp programming details for programming the configuration registers, including the serial pattern with the icsp command code, which must be transmitted, lsb first, using the pgcx and pgdx pins (see figure 3-2 ). in step 1 of table 3-7 , the reset vector is exited. in step 2, the nvmcon register is initialized for programming code memory. in step 3, the 24-bit starting destination address for programming is loaded into the tblpag register and w7 register. table 3-6: default values for configuration register serial instruction note: the tblpag register is hard-coded to 0xf8 (the upper byte address of all locations of the configuration registers). note: the tblpag register must be loaded with f8h. configuration registers value fgs 03h foscsel 87h fosc ffh fwdt dfh fpor fbh ficd (1) c3h fds ffh note 1: the configuration register, ficd, is a reserved location and should be programmed with the default value given above. pic24fxxka2xx ds39991a-page 14 ? 2010 microchip technology inc. table 3-7: serial instruction executio n for writing configuration registers command (binary) data (hex) command (binary) step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize the write pointer (w7) for the tblwt instruction. 0000 200007 mov #0x0000, w7 step 3: set the nvmcon register to program configuration registers. 0000 0000 24004a 883b0a mov #0x4004, w10 mov w10, nvmcon step 4: initialize the tblpag register. 0000 0000 200f80 880190 mov #0xf8, w6 mov w0, tblpag step 5: load the configuration register data to w6. 0000 2xxxx6 mov # ? 2010 microchip technology inc. ds39991a-page 15 pic24fxxka2xx table 3-8: pic24fxxka2xx family configuration bits description bit field register description boren<1:0> fpor<1:0> brown-out reset enable bits 11 = brown-out reset is enabled in hardware; sboren bit is disabled 10 = brown-out reset is enabled only while device is active and disabled in sleep; sboren bit is disabled 01 = brown-out reset controlled with the sboren bit setting 00 = brown-out reset is disabled in hardware; sboren bit is disabled borv<1:0> fpor<6:5> brown-out reset voltage bits 11 = v bor set to 1.8v min 10 = v bor set to 2.0v min 01 = v bor set to 2.7v min 00 = downside protection on por enabled ? ?zero-power? selected dswdten fds<7> deep sleep watchdog timer enable bit 1 = dswdt is enabled 0 = dswdt is disabled dswdtps<3:0> fds<3:0> deep sleep watchdog timer postscale select bits the dswdt prescaler is 32; this creates an approximate base time unit of 1ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) dszpbor fds<6> deep sleep zero-power bor enable bit 1 = zero-power bor is enabled in deep sleep 0 = zero-power bor is disabled in deep sleep (does not affect operation in non deep sleep modes) fcksm<1:0> fosc<7:6> clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled fnosc<2:0> foscsel<2:0> oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator with divide-by-n with pll module (frcdiv+pll) 010 = primary oscillator (xt, hs, ec) 011 = primary oscillator with pll module (hs+pll, ec+pll) 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = reserved; do not use 111 = fast rc oscillator with divide-by-n (frcdiv) note 1: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. pic24fxxka2xx ds39991a-page 16 ? 2010 microchip technology inc. fwpsa fwdt<4> wdt prescaler 1 = wdt prescaler ratio of 1:128 0 = wdt prescaler ratio of 1:32 fwdten fwdt<7> watchdog timer enable bit 1 = wdt is enabled 0 = wdt is disabled (control is placed on the swdten bit) gss0 fgs<1> general segment code flash code protection bit 1 = no protection 0 = standard security is enabled gwrp fgs<0> general segment code flash write protection bit 1 = general segment may be written 0 = general segment is write-protected ics<1:0> ficd<1:0> icd pin placement select bit 11 = reserved; do not use 10 = pgec2/pged2 are us ed for icsp programming 01 = pgec3/pged3 are us ed for icsp programming 00 = reserved; do not use ieso foscsel<7> internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up enabled) 0 = internal external switchover mode is disabled (two-speed start-up disabled) mclre (1) fpor<7> mclr pin enable bit (1) 1 = mclr pin is enabled; ra5 input pin is disabled 0 = ra5 input pin is enabled; mclr is disabled osciofnc fosc<2> clko enable configuration bit 1 = clko output signal is active on the osco pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmd<1:0> = 11 or 00 ) 0 = clko output is disabled poscmd<1:0> fosc<1:0> primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected (4 mhz-25 mhz) 01 = xt oscillator mode selected (100 khz-4 mhz) 00 = external clock mode selected poscfreq<1:0> fosc<4:3> primary oscillator frequency range configuration bits 11 = primary oscillator/external clock input frequency is greater than 8 mhz 10 = primary oscillator/external clock input frequency is between 100 khz and 8mhz 01 = primary oscillator/external clock input frequency is less than 100 khz 00 = reserved; do not use pwrten fpor<3> power-up timer enable bit 0 = pwrt is disabled 1 = pwrt is enabled soscsel fosc<5> secondary oscillator select bit 1 = secondary oscillator is configured for high-power operation 0 = secondary oscillator is configured for low-power operation table 3-8: pic24fxxka2xx family config uration bits description (continued) bit field register description note 1: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. ? 2010 microchip technology inc. ds39991a-page 17 pic24fxxka2xx wdtps<3:0> fwdt<3:0> watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 ? ? ? 0001 =1:2 0000 =1:1 windis fwdt<6> windowed watchdog timer disable bit 1 = standard wdt selected; windowed wdt is disabled 0 = windowed wdt is enabled table 3-8: pic24fxxka2xx family config uration bits description (continued) bit field register description note 1: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. pic24fxxka2xx ds39991a-page 18 ? 2010 microchip technology inc. 3.8 reading code memory to read the code memory, execute a series of tblrd instructions and clock out the data using the regout command. table 3-9 provides the icsp programming details for reading code memory. in step 1, the reset vector is exited. in step 2, the 24-bit starting source address for reading is loaded into the tblpag register and the w6 register. the upper byte of the starting source address is stored in tblpag, and the lower 16 bits of the source address are stored in w6. to minimize the reading time, the packed instruction word format, which was used for writing, is also used for reading (see figure 3-7 ). in step 3, the write pointer, w7, is initialized. in step 4, two instruction words are read from code memory, and clocked out of the device through the visi register, using the regout command. step 4 is repeated until the required amount of code memory is read. table 3-9: serial instruction execution for reading code memory command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 200xx0 880190 2xxxx6 mov # ? 2010 microchip technology inc. ds39991a-page 19 pic24fxxka2xx 3.9 reading configuration memory the procedure for reading a configuration register is the same as reading the code memory. the only difference is that the 16-bit data words are read (with the upper byte read being all ? 0 ?s) instead of the 24-bit words. there are eight configuration registers and they are read, one register at a time. table 3-10 provides the icsp programming details for reading all of the configuration registers. note: the tblpag register should be hard-coded to 0xf8 (the upper byte address of the configuration register) and the read pointer, w6, is initialized to 0x00h. table 3-10: serial instruction execution for reading all the configuration registers command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag, the read pointer (w6) and the write pointer (w7) for tblrd instruction. 0000 0000 0000 0000 0000 200f80 880190 200007 207847 000000 mov #0xf8, w0 mov w0, tblpag mov #0x0000,w6 mov #visi, w7 nop step 3: read the configuration register and write it to the visi register (located at 784h), and clock out the visi register using the regout command. 0000 0000 0000 0001 ba0bb6 000000 000000 pic24fxxka2xx ds39991a-page 20 ? 2010 microchip technology inc. 3.10 verifying code memory and configuration registers to verify the code memory, read the code memory space and compare it with the copy held in the programmer?s buffer. figure 3-9 illustrates the verify process flowchart. memory reads occur 1 byte at a time, hence 2 bytes must be read to compare with the word in the programmer?s buffer. refer to section 3.8 ?reading code memory? for implementation details of reading code memory. on the same lines, the data eeprom and configuration registers can be verified. figure 3-9: verify code memory flow 3.11 exiting icsp mode exit the program/verify mode by removing v ih from mclr /v pp as illustrated in figure 3-10 . the only requirement to exit is that an interval of p16 should elapse between the last clock and the program signals on pgcx and pgdx before removing v ih . figure 3-10: exiting icsp? mode note: code memory should be verified immediately after writing if code protection is enabled. since configuration registers include the device code protection bit, the device will not be readable or verifiable if a device reset occurs after the code-protect bits are set (value = 0 ). read low byte read high byte does word = expect data? all code memory verified? no yes no set tblptr = 0 start yes end with post-increment with post-increment failure report error mclr /v pp p16 pgdx pgd = input pgcx v dd v ih /v ihh v ih p17 ? 2010 microchip technology inc. ds39991a-page 21 pic24fxxka2xx 4.0 device id the device id region of memory can be used to determine the mask, variant and manufacturing information about the device. the device id region is 2 x 16 bits and it can be read using the readc command. this region of memory is read-only and can also be read when code protection is enabled. ta b l e 4 - 1 provides the device id for each device; ta b l e 4 - 2 provides the device id registers; ta b l e 4 - 3 describes the bit field of each register. table 4-1: device ids 4.1 checksums 4.1.1 checksum computation checksums for the pic24fxxka2xx family are 16 bits. the checksum is calculated by summing the following: ? contents of the code memory locations ? contents of the configuration registers table 4-4 describes how to calculate the checksum for each device. all memory locations are summed, one byte at a time, using only their native data size. more specifically, configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored) while the code memory is summed by adding all three bytes of the code memory. table 4-2: pic24fxxka2xx device id registers device id devid PIC24F04KA200 0d02h pic24f04ka201 0d00h address name bit 15 14131211109876543210 ff0000h devid famid<7:0> dev<7:0> ff0002h devrev ? rev<3:0> table 4-3: device id bits description bit field register description famid<7:0> devid encodes the family id of the device. dev<7:0> devid encodes the individual id of the device. rev<3:0> devrev encodes the revision number of the device. table 4-4: checksum computation device read code protection checksum computation erased checksum value chip checksum with 0xaaaaaa at 0x00 location and at last location pic24f04kaxxx disabled cfgb + sum (0:000afe) 0x74b4 0x72b6 enabled 0 0x0000 0x0000 legend: item description sum[a:b] = byte sum of locations, a to b inclusive (all 3 bytes of code memory) cfgb = configuration block (masked), byte sum of (fgs & 0x0003 + foscsel & 0x0087 + fosc & 0x00df + fwdt & 0x00df + fpor & 0x00fb + ficd & 0x00c3 + fds & 0x00ff) pic24fxxka2xx ds39991a-page 22 ? 2010 microchip technology inc. 5.0 ac/dc characteristics and timing requirements table 5-1: standard operating conditions standard operating conditions operating temperature: 0 ? c to +70 ? c and programming: +25 ? c is recommended. param no. symbol characteristic min max units conditions d111 v dd supply voltage during programming v ddcore 3.60 v normal programming d112 i pp programming current on mclr ?50 ? a? d113 i ddp supply current during programming ? 2 ma ? d031 v il input low voltage v ss 0.2 v dd v? d041 v ih input high voltage 0.8 v dd v dd v? d042 v ihh programing voltage on v pp v dd +1.5 9 v ? d080 v ol output low voltage ? 0.4 v i ol = 8.5 ma @ 3.6v d090 v oh output high voltage 1.4 ? v i oh = -3.0 ma @ 3.6v d012 c io capacitive loading on i/o pin (pgdx) ? 50 pf to meet ac specifications p1 t pgc serial clock (pgcx) period 125 ? ns ? p1a t pgcl serial clock (pgcx) low time 50 ? ns ? p1b t pgch serial clock (pgcx) high time 50 ? ns ? p2 t set 1 input data setup time to serial clock ? 15 ? ns ? p3 t hld 1 input data hold time from pgcx ?? 15 ? ns ? p4 t dly 1 delay between 4-bit command and command operand 40 ? ns ? p4a t dly 1 a delay between 4-bit command operand and the next 4-bit command 40 ? ns ? p5 t dly 2 delay between last pgcx ? of command byte and first pgcx ? of read of data word 20 ? ns ? p6 t set 2v dd ?? setup time to mclr ? 100 ? ns ? p7 t hld 2 input data hold time from mclr ? v pp ? (from v ihh to v ih ) 25 ? ms ? p10 t dly 6 pgcx low time after programming 400 ? ns ? p11 t dly 7 chip erase time 5 ? ms ? p12 t dly 10 page (4 rows) erase time 5 ? ms ? p13 t dly 9 row programming time 2 ? ms ? p14 t r mclr rise time to enter icsp? mode ? 1.0 ? s? p15 t valid data out valid from pgcx ? 10 ? ns ? p16 t dly 10 delay between last pgcx ? and mclr ? 0?s ? p17 t hld 3mclr ?? to v dd ? ?100ns ? p18 t key 1 delay between first mclr ?? and first pgcx ?? for key sequence on pgdx 1?ms ? p19 t key 2 delay between last pgcx ?? for key sequence on pgdx and second mclr ?? 1?ms ? ? 2010 microchip technology inc. ds39991a-page 23 pic24fxxka2xx appendix a: revision history rev a document (9/2010) original version of this document; takes all information specific to pic24xxka20x family devices, originally found in ds39919, and created a new specification. no technical information regarding the devices or their programming has changed. pic24fxxka2xx ds39991a-page 24 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds39991a-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-604-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds39991a-page 26 ? 2010 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-213-7830 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 08/04/10 |
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